1. Field
Various features relate to integrated circuits (ICs), and more particularly to multi-chip ICs and methods for making the same.
2. Background
The ever increasing demand for smaller, lighter, and faster portable electronic devices, such as mobile phones and laptop computers, has forced the electronics industry to create circuit components that feature greater capacity and performance, but smaller dimensions. For example, portable devices may now contain IC packages having two or more semiconductor dies stacked vertically and encased within the same molding compound of the IC package. Such multi-chip IC packages may be commonly referred to as “system-in-packages” (SIP) and “chip stack multi-chip modules” (MCM).
FIG. 1 illustrates a schematic, cross-sectional side view of an SIP 100 found in the prior art. The SIP 100 includes two IC dies 102, 104 that are stacked on top of each other. The top IC die 102 may be, for example, a memory circuit, and the bottom IC die 104 may be, for example, a processing circuit. The length and/or width of the top die 102 is larger than the length and/or width of the bottom die 104, and generally, the top die 102 may have a surface area that is greater than the bottom 104. The two dies 102, 104 are stacked on top of each other and encased within a single molding compound 106. The active surface 110 of the top die 102 is electrically coupled to a laminate substrate 108 via a plurality of soldering bumps 112a and conductive pillars 112b. The active surface 114 of the bottom die 104 is electrically coupled to the substrate 108 via another plurality of soldering bumps 116. In this fashion, both dies 102, 104 are electrically coupled to the substrate 108 in a flip-chip fashion, and communicate with each other through electrical connections (not shown) within the laminate substrate 108. The package 100 may be mounted onto a motherboard (e.g., PCB board) through a ball grid array or pin grid array structure (not shown).
FIG. 2 illustrates a schematic, top view of the SIP package 100 with the molding compound 106 removed thereby exposing the top IC die 102 underneath. The top die 102 has a length lA and a width wA. FIG. 3 illustrates a schematic, bottom view of the SIP package 100. The substrate 108 and molding compound 106 have been omitted for clarity thereby exposing the top die 102 having the soldering bumps 112a and the bottom die 104 having the soldering bumps 116.
The top IC die 102 will have limited speed, performance, reliability, and/or throughput due to its relatively larger size (e.g., larger surface area and/or greater dimensions along its length and/or width) compared to the bottom IC die 104. For example, the top die 102 may suffer from crosstalk and electromagnetic interference (EMI) effects among the various IC components located on its active surface 110. These undesirable effects limit the clock speed at which the top die 102, for example volatile dynamic random access memory (DRAM), can reliability operate due to clock signal jitter.
Moreover, the larger, top die 102 is more prone to failure from open solder joints due to warpage effects. FIG. 4 illustrates a schematic, cross sectional side view of the SIP 100 (bottom die 104 and associated soldering bumps 116 have been omitted for clarity) where the substrate 108 has undergone significant concave warpage. According to the illustrated example, although some of the soldering bumps 402 near the corners 403 of the top die 102 remain in electrical contact with the substrate 108, other soldering bumps 404 near the center edge 405 of the top die 102 have separated away from the substrate 108 and are no longer in electrical contact with the substrate 108. Thus, warpage of the substrate 108 may lead to IC package 100 failure because critical connections between the top die 102 and the substrate 108 may become open/disconnected.
Therefore, there is a need for advanced multi-chip IC package designs that improve circuit speed and performance, and also protect against IC package failure due to warpage.